technical data 540 octal 3-state bus transceivers and d flip-flops high-speed silicon-gate cmos the in74act652 is identical in pinout to the ls/als652, hc/hct652. the in74act652 may be used as a level converter for interfacing ttl or nmos outputs to high speed cmos inputs. these devices consists of bus transceiver circuits, d-type flip-flop, and control circuitry arranged for multiplex transmission of data directly from the data bus or from the internal storage registers. direction and output enable are provided to select the read-time or stored data function. data on the a or b data bus, or both, can be stored in the internal d flip-flops by low-to-high transitions at the appropriate clock pins (a-to-b clock or b-to-a clock) regardless of the select or enable or enable control pins. when a-to-b source and b-to-a source are in the real-time transfer mode, it is also possible to store data without using the internal d-type flip-flops by simultaneously enabling direction and output enable. in this configuration each output reinforces its input. thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. the in74act652 has noninverted outputs. ? ttl/nmos compatible input levels ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 4.5 to 5.5 v ? low input current: 1.0 a; 0.1 a @ 25 c ? outputs source/sink 24 ma in74act652 ordering information in74act652n plastic IN74ACT652DW soic t a = -40 to 85 c for all packages pin assignment logic diagram pin 24=v cc pin 12 = gnd
in74act652 541 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +7.0 v v in dc input voltage (referenced to gnd) -0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 4.5 5.5 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t j junction temperature (pdip) 140 c t a operating temperature, all package types -40 +85 c i oh output current - high -24 ma i ol output current - low 24 ma t r , t f input rise and fall time * (except schmitt inputs) v cc =4.5 v v cc =5.5 v 0 0 10 8.0 ns/v * v in from 0.8 v to 2.0 v this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
in74act652 542 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limits symbol parameter test conditions v 25 c-40 c to 85 c unit v ih minimum high-level input voltage v out =0.1 v or v cc -0.1 v 4.5 5.5 2.0 2.0 2.0 2.0 v v il maximum low - level input voltage v out =0.1 v or v cc -0.1 v 4.5 5.5 0.8 0.8 0.8 0.8 v v oh minimum high-level output voltage i out -50 a 4.5 5.5 4.4 5.4 4.4 5.4 v * v in =v ih or v il i oh =-24 ma i oh =-24 ma 4.5 5.5 3.86 4.86 3.76 4.76 v ol maximum low-level output voltage i out 50 a 4.5 5.5 0.1 0.1 0.1 0.1 v * v in =v ih or v il i ol =24 ma i ol =24 ma 4.5 5.5 0.36 0.36 0.44 0.44 i in maximum input leakage current v in =v cc or gnd 5.5 0.1 1.0 a ? i cct additional max. i cc /input v in =v cc - 2.1 v 5.5 1.5 ma i oz maximum three- state leakage current v in (oe)= v ih or v il v in =v cc or gnd v out =v cc or gnd 5.5 0.6 6.0 a i old +minimum dynamic output current v old =1.65 v max 5.5 75 ma i ohd +minimum dynamic output current v ohd =3.85 v min 5.5 -75 ma i cc maximum quiescent supply current (per package) v in =v cc or gnd 5.5 8.0 80 a * all outputs loaded; thresholds on input associated with output under test. +maximum test duration 2.0 ms, one output loaded at a time.
in74act652 543 ac electrical characteristics (v cc =5.0 v 10%, c l =50pf,input t r =t f =3.0 ns) guaranteed limits symbol parameter 25 c-40 c to 85 c unit min max min max t plh propagation delay, a-to-b clock or b-to-a clock to a or b data port (figure 1) 4.0 14.5 3.5 16.5 ns t phl propagation delay, a-to-b clock or b-to-a clock to a or b data port (figure 1) 3.5 14.5 3.0 16.5 ns t plh propagation delay, input a to output b or input b to output a (figures 2,3) 2.5 11.5 2.0 13.0 ns t phl propagation delay, input a to output b or input b to output a (figures 2,3) 2.5 11.5 2.0 13.0 ns t plh propagation delay, a-to-b source or b-to-a source to a or b data port (figure 4) 2.5 12.0 2.0 13.5 ns t phl propagation delay, a-to-b source or b-to-a source to a or b data port (figure 4) 3.0 12.0 2.5 13.5 ns t pzh propagation delay, output enable to a data port (figure 5) 2.0 11.5 1.5 13.0 ns t pzl propagation delay, output enable to a data port (figure 5) 2.5 11.5 2.0 13.0 ns t phz propagation delay, output enable to a data port (figure 5) 3.0 13.0 2.5 14.0 ns t plz propagation delay, output enable to a data port (figure 5) 2.5 12.5 2.0 14.0 ns t pzh propagation delay, direction to b data port (figure 6) 2.5 12.0 2.0 13.5 ns t pzl propagation delay, direction to b data port (figure 6) 2.5 12.0 2.0 13.5 ns t phz propagation delay, direction to b data port (figure 6) 3.5 13.5 3.0 14.5 ns t plz propagation delay, direction to b data port (figure 6) 3.0 13.5 2.5 15.0 ns c in maximum input capacitance 4.5 4.5 pf c out input/output capacitance 15 15 pf typical @25 c,v cc =5.0 v c pd power dissipation capacitance 60 pf
in74act652 544 timing requirements (c l =50pf,input t r =t f =3.0 ns) v cc * guaranteed limits symbol parameter v 25 c-40 c to 85 c unit t su minimum setup time, a or b data port to a- to-b clock or b-to-a clock (figure 7) 5.0 7.0 8.0 ns t h minimum hold time, a-to-b clock or b-to-a clock to a or b data port (figure 7) 5.0 2.5 2.5 ns t w minimum pulse width, a-to-b clock or b-to-a clock (figure 7) 5.0 6.0 7.0 ns timing diagram
in74act652 545 function table dir. oe cab cba sab sba a b function inputs inputs both the a bus and the b bus are inputs. l h x x x x z z the output functions of the a and b bus are disabled. x x inputs inputs both the a and b bus are used for inputs to the internal flip-flops. data at the bus will be stored on low to high transition of the clock inputs. outputs inputs the a bus are outputs and the b bus are inputs. x * xxl l h l h the data at the b bus are displayed at the a bus. llx * xl l h l h the data at the b bus are displayed at the a bus. the data of the b bus are stored to the internal flip-flops on low to high transition of the clock pulse. x * x x h qn x the data stored to the internal flip-flops, are displayed at the a bus. x * xh h l h l the data at the b bus are stored to the internal flip-flops on low to high transition of the clock pulse. the states of the internal flip-flops output directly to the a bus. inputs outputs the a bus are inputs and the b bus are outputs. xx * lx l h l h the data at the a bus are displayed at the b bus. hh x * lx l h l h the data at the b bus are displayed at the a bus. the data of the b bus are stored to the internal flip-flops on low to high transition of the clock pulse. xx * h x x qn the data stored to the internal flip-flops are displayed at the b bus. x * hx l h l h the data at the a bus are stored to the internal flip-flops on low to high transition of the clock pulse. the states of the internal flip-flops output directly to the b bus. outputs outputs both the a bus and the b bus are outputs h l x x h h qn qn the data stored to the internal flip-flops are displayed at the a and b bus respectively. h h qn qn the output at the a bus are displayed at the b bus, the output at the b bus are displayed at the a bus respec. x : don?t care z : high impedance qn : the data stored to the internal flip-flops by most recent low to high transition of the clock inputs * : the data at the a and b bus will be stored to the internal flip-flops on every low to transition of the clock inputs
in74act652 546 switching diagrams figure 1. switching waveforms figure 2. a data port = input, b data port = output figure 3. a data port = output, b data port = input figure 4. switching waveforms figure 5. switching waveforms figure 6. switching waveforms figure 7. switching waveforms
in74act652 547 expanded logic diagram
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